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general description the hi-3210 from holt integrated circuits is a single chip cmos data management ic capable of managing, storing and forwarding avionics data messages between eight arinc 429 receive channels and four arinc 429 transmit channels. the arinc 429 buses may be operated independently, allowing a host cpu to send and receive data on multiple buses, or the hi-3210 can be programmed to automati- cally re-format, re-label, re-packetize and re-transmit data from arinc 429 receive buses to arinc 429 transmit buses. a 32k x 8 on-board memory allows received data to be logically organized and automatically updated as new arinc 429 labels are received. an auto-initialization feature allows configuration informa- tion to be up-loaded from an external eeprom on reset to facilitate rapid start-up or operation without a host cpu. the hi-3210 interfaces directly with holt?s hi-8448 octal arinc 429 receiver ic and hi-8592 or hi-8596 arinc 429 line drivers. features ? ? ? ? ? ? ? eight arinc 429 receive channels four arinc 429 transmit channels 32kb on chip user-configurable data storage memory programmable received data filtering programmable transmission schedulers for periodic arinc 429 broadcasting spi host cpu interface auto-initialization feature allows power-on configuration or independent operation without cpu (ds3210 rev. new) 05/11 arinc 429 data management engine / octal receiver / quad transmitter may 2011 hi-3210 pin configuration 64 - pin plastic quad flat pack (pqfp) (see ordering information for additional pin configurations) hi-3210pqi & hi-3210pqt aack 1 arxbit6 2 aint 3 arxbit7 4 scanshift 5 arx2n 6 arx3p 7 vdd 8 gnd 9 arx3n 10 arx4p 11 arx4n 12 arx5p 13 arx5n 14 arx6p 15 arx6n 16 48 arxbit3 47 atxslp0 46 atx0n 45 atx0p 44 atx1n 43 atx1p 42 atxslp1 41 vdd 40 gnd 39 arxbit2 38 atxslp2 37 atx2n 36 atx2p 35 atx3n 34 atx3p 33 atxslp3 64 arx2p 63 arx1n 62 arx1p 61 arx0n 60 arx0p 59 scanen 58 arxbit5 57 ready 56 esclk 55 emosi 54 53 emiso 52 run 51 arxbit4 50 atxmsk 49 mrst ecsb arx7p 17 arx7n 18 mode0 19 mode1 20 mclk 21 mode2 22 arxbit0 23 vdd 24 gnd 25 arxbit1 26 hmiso 27 hsclk 28 hmosi 29 30 mint 31 mintack 32 hcsb application cpu arinc 429 8 x receive arinc 429 4 x transmit hi-8448 hi-3210 memory controller
hi-3210 holt integrated circuits 2 block diagram arinc 429 receive data memory 0 1k x 8 8 x arinc 429 receive buses receiver 0 message 32 ? ? ? message 2 message 1 label filter filter table 0 channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 32 x 32 fifo hi-3210 spi hcsb hsclk hmosi hmiso host cpu eeprom spi ecsb esclk emosi emiso auto-initialization eeprom 4 x arinc 429 transmit buses transmitter 0 transmit timer arinc 429 transmit scheduler 0 arinc 429 descriptor table 0 channel 0 channel 1 channel 2 channel 3 arinc 429 interrupt handler programmable interrupts aack aint mint mintack arinc 429 bit match arxbit4 arxbit3 arxbit2 arxbit1 arxbit6 arxbit5 arxbit7 arxbit0
hi-3210 holt integrated circuits 3 application overview the hi-3210 is a flexible device for managing arinc 429 communications and data storage in many avionics applications. the device architecture centers around a 32k x 8 static ram used for data storage, data filtering tables and table-driven transmission schedulers. once configured, the device can operate autonomously without a host cpu, negating the need for software development or do-178 certification. configuration data may be uploaded into the device from an external eeprom, following system reset. the device supports up to eight arinc 429 receive channels. received data is stored in on-chip ram organized by channel number and label. the data table continually updates as new labels arrive. programmable interrupts and filters alert the host subsystem to labels of interest. each arinc 429 receive channel also includes a 32 message deep fifo allowing selected label data to be queued for subsequent host access. the hi-3210 includes four independent arinc 429 transmit channels. transmission may be controlled entirely by an external cpu, or autonomously by programming one or more of the four on-chip arinc 429 transmit schedulers. these allow periodic transmission to occur without cpu. source data for transmission may be selected from ram based tables of constants and / or from the received channel data. powerful options exist for constructing arinc 429 labels as well as controlling their timing and conditional transmission. even when running under the control of schedulers, the host cpu may insert new labels for transmission at will. the following examples show five possible configurations of how the hi-3210 may be used: example 1. arinc 429 data reception using on-chip ram 8k x 8 ram 8 x arinc 429 receive buses spi channel 0, label ff ? ? ? channel 0, label 01 channel 0, label 00 channel 1, label ff ? ? ? channel 1, label 01 channel 1, label 00 channel 2, label ff ? ? ? channel 2, label 01 channel 2, label 00 channel 3, label ff ? ? ? channel 3, label 01 channel 3, label 00 channel 4, label ff ? ? ? channel 4, label 01 channel 4, label 00 channel 5, label ff ? ? ? channel 5, label 01 channel 5, label 00 channel 6, label ff ? ? ? channel 6, label 01 channel 6, label 00 channel 7, label ff ? ? ? channel 7, label 01 channel 7, label 00 arinc 429 receive interrupt table aint aack hcsb hsclk hmosi hmiso receiver 7 receiver 6 receiver 5 receiver 4 receiver 3 receiver 2 receiver 1 receiver 0 host cpu hi-3210
holt integrated circuits 4 hi-3210 example 3. arinc 429 data transmission directly from cpu transmitter 0 spi hcsb hsclk hmosi hmiso transmitter 2 transmitter 1 transmitter 3 host cpu 4 x arinc 429 transmit buses hi-3210 8 x arinc 429 receive buses receiver 0 fifo status hi-3210 message 32 ? ? ? message 2 message 1 label filter filter table 0 spi arinc 429 receive fifo interrupt control aint aack hcsb hsclk hmosi hmiso host cpu fifo empty fifo threshold fifo full channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 32 x 32 fifo example 2. arinc 429 data reception using on-chip filters and fifos example 4. arinc 429 data transmission using on-chip schedulers transmit scheduler 0 ram descriptor table 3 4 x arinc 429 transmit buses transmitter 0 descriptor table 2 descriptor table 1 descriptor table 0 transmit timer channel 0 channel 1 channel 2 channel 3 eeprom spi ecsb esclk emosi emiso auto-initialization eeprom hi-3210 spi hcsb hsclk hmosi hmiso host cpu
holt integrated circuits 5 hi-3210 transmit scheduler 3 4 x arinc 429 transmit buses transmitter 3 descriptor table 3 transmit timer eeprom spi ecsb esclk emosi emiso auto-initialization eeprom hi-3210 example 5. autonomous arinc 429 data concentrator / repeater 8 x arinc 429 receive buses channel 0, label ff ? ? ? channel 0, label 01 channel 0, label 00 channel 1, label ff ? ? ? channel 1, label 01 channel 1, label 00 channel 2, label ff ? ? ? channel 2, label 01 channel 2, label 00 channel 3, label ff ? ? ? channel 3, label 01 channel 3, label 00 channel 4, label ff ? ? ? channel 4, label 01 channel 4, label 00 channel 5, label ff ? ? ? channel 5, label 01 channel 5, label 00 channel 6, label ff ? ? ? channel 6, label 01 channel 6, label 00 channel 7, label ff ? ? ? channel 7, label 01 channel 7, label 00 receiver 7 receiver 6 receiver 5 receiver 4 receiver 3 receiver 2 receiver 1 receiver 0 transmit scheduler 2 transmitter 2 descriptor table 2 transmit timer transmit scheduler 1 transmitter 1 descriptor table 1 transmit timer transmit scheduler 0 transmitter 0 descriptor table 0 transmit timer
holt integrated circuits 6 hi-3210 pin descriptions signal function description aack input arinc 429 receiver interrupt acknowledge aint output arinc 429 receiver interrupt arx0n input arinc 429 rx negative data input for channel 0 arx0p input arinc 429 rx positive data input for channel 0 arx1n input arinc 429 rx negative data input for channel 1 arx1p input arinc 429 rx positive data input for channel 1 arx2n input arinc 429 rx negative data input for channel 2 arx2p input arinc 429 rx positive data input for channel 2 arx3n input arinc 429 rx negative data input for channel 3 arx3p input arinc 429 rx positive data input for channel 3 arx4n input arinc 429 rx negative data input for channel 4 arx4p input arinc 429 rx positive data input for channel 4 arx5n input arinc 429 rx negative data input for channel 5 arx5p input arinc 429 rx positive data input for channel 5 arx6n input arinc 429 rx negative data input for channel 6 arx6p input arinc 429 rx positive data input for channel 6 arx7n input arinc 429 rx negative data input for channel 7 arx7p input arinc 429 rx positive data input for channel 7 arxbit0-7 outputs arinc 429 received payload bit monitor pins 0 through 7 atx0n output arinc 429 tx channel 0 negative data output to line driver atx0p output arinc 429 tx channel 0 positive data output to line driver atx1n output arinc 429 tx channel 1 negative data output to line driver atx1p output arinc 429 tx channel 1 positive data output to line driver atx2n output arinc 429 tx channel 2 negative data output to line driver atx2p output arinc 429 tx channel 2 positive data output to line driver atx3n output arinc 429 tx channel 3 negative data output to line driver atx3p output arinc 429 tx channel 3 positive data output to line driver atxmsk input turn off arinc 429 transmit pins (holds txna/b pins zero) atxslp0 output arinc 429 tx channel 0 data rate select output . 1 = high speed , 0 = low speed atxslp1 output arinc 429 tx channel 1 data rate select output . 1 = high speed , 0 = low speed atxslp2 output arinc 429 tx channel 2 data rate select output . 1 = high speed , 0 = low speed atxslp3 output arinc 429 tx channel 3 data rate select output . 1 = high speed , 0 = low speed ecsb output spi chip select for auto-initialization eeprom emiso input spi serial data input from auto-inialization eeprom emosi output spi serial data output to auto-initialization eeprom esclk output spi clock for auto-initialization eeprom gnd power chip 0v supply hcsb input chip select. data is shifted into hmosi and out of hmiso when hcsb is low hmiso output host cpu spi interface serial data output hmosi input host cpu spi interface serial data input hsclk input spi clock. data is shifted into or out of the spi interface using hsclk mclk input master 48 mhz and reference clock for arinc 429 bus bit timing mint output programmable event interrupt output mintack input programmable event interrupt acknowledge mode2:0 inputs mode2 through mode0 define hi-3210 start-up and initialization mode mrst input master reset to hi-3210 active high prog (mode0) input multiplexed with mode0 pin, prog initiates hi-3210 auto-initialization eeprom programming routine ready output ready goes high when post-reset initialization is complete run input master enable signal for arinc 429 transmit schedulers scanen reserved connect to gnd scanshift reserved connect to gnd vdd power 3.3v power supply
hi-3210 memory map arinc 429 receive data reserved reserved arinc 429 tx0 transmit schedule table reserved look-up tables 0x0000 0x2000 0x1fff 0x2fff 0x3000 0x33ff 0x3400 0x3fff 0x4000 0x47ff arinc 429 tx1 transmit schedule table arinc 429 tx2 transmit schedule table arinc 429 log fifo space arinc 429 tx3 transmit schedule table 0x4800 0x4fff 0x5000 0x57ff 0x5800 0x5fff 0x6000 0x79ff 0x7bff configuration registers 0x8000 0x8xxx arinc 429 rx enable map arinc 429 rx interrupt map 0x7a00 0x7aff 0x7b00 0x7bff shaded area user - programmed non-shaded area data storage reserved 0x7c00 0x7fff holt integrated circuits 7 0x7a00 hi-3210
hi-3210 register map address r/w register mnemonic description 0x8000 r* arinc 429 rx pending interrupt apir defines channel(s) with pending interrupt 0x8001 r arinc 429 rx interrupt address 0 aiar0 arinc 429 interrupt vector channel 0 0x8002 r arinc 429 rx interrupt address 1 aiar1 arinc 429 interrupt vector channel 1 0x8003 r arinc 429 rx interrupt address 2 aiar2 arinc 429 interrupt vector channel 2 0x8004 r arinc 429 rx interrupt address 3 aiar3 arinc 429 interrupt vector channel 3 0x8005 r arinc 429 rx interrupt address 4 aiar4 arinc 429 interrupt vector channel 4 0x8006 r arinc 429 rx interrupt address 5 aiar5 arinc 429 interrupt vector channel 5 0x8007 r arinc 429 rx interrupt address 6 aiar6 arinc 429 interrupt vector channel 6 0x8008 r arinc 429 rx interrupt address 7 aiar7 arinc 429 interrupt vector channel 7 0x8009 - reserved 0x800a r* pending interrupt register pir indicates interrupt type 0x800b r reserved 0x800c r muxed fifo flags amff arinc 429 multiplexed fifo flags 0x800d r arinc 429 tx ready bits atrb arinc 429 transmitter ready flags 0x800e r master status register msr indicates hi-3200 current status 0x800f r/w master control register mcr hi-3200 global configuration 0x8010 r/w arinc 429 rx control register 0 arxc0 configures arinc 429 receive channel 0 0x8011 r/w arinc 429 rx control register 1 arxc1 configures arinc 429 receive channel 1 0x8012 r/w arinc 429 rx control register 2 arxc2 configures arinc 429 receive channel 2 0x8013 r/w arinc 429 rx control register 3 arxc3 configures arinc 429 receive channel 3 0x8014 r/w arinc 429 rx control register 4 arxc4 configures arinc 429 receive channel 4 0x8015 r/w arinc 429 rx control register 5 arxc5 configures arinc 429 receive channel 5 0x8016 r/w arinc 429 rx control register 6 arxc6 configures arinc 429 receive channel 6 0x8017 r/w arinc 429 rx control register 7 arxc7 configures arinc 429 receive channel 7 0x8018 r/w arinc 429 tx control register 0 atxc0 configures arinc 429 transmit channel 0 0x8019 r/w arinc 429 tx control register 1 atxc1 configures arinc 429 transmit channel 1 0x801a r/w arinc 429 tx control register 2 atxc2 configures arinc 429 transmit channel 2 0x801b r/w arinc 429 tx control register 3 atxc3 configures arinc 429 transmit channel 3 0x801c r/w arinc 429 tx repetition rate 0 atxrr0 sets sequence repeat time for arinc tx0 0x801d r/w arinc 429 tx repetition rate 1 atxrr1 sets sequence repeat time for arinc tx1 0x801e r/w arinc 429 tx repetition rate 2 atxrr2 sets sequence repeat time for arinc tx2 0x801f r/w arinc 429 tx repetition rate 3 atxrr3 sets sequence repeat time for arinc tx3 0x8020 r/w arinc 429 rx interrupt mask aimr enables interrupts on aint pin 0x8021 r/w arinc 429 rx fifo threshold value aftv sets flag value for arinc 429 receive fifo 0x8022 r/w arinc 429 loopback aloop sets loop-back self-test mode 0x8029 r arinc 429 rx fifo full flag afff indicates which fifos are full 0x802a r arinc 429 rx fifo threshold flag aftf indicates which fifos hold > (thresh) messages 0x802b r arinc 429 rx fifo not empty flag ffne indicates which receive fifos hold data 0x802c r arinc 429 tx sequence pointer 0 atxsp0 current address of arinc transmit sequence 0 0x802d r arinc 429 tx sequence pointer 1 atxsp1 current address of arinc transmit sequence 1 0x802e r arinc 429 tx sequence pointer 2 atxsp2 current address of arinc transmit sequence 2 0x802f r arinc 429 tx sequence pointer 3 atxsp3 current address of arinc transmit sequence 3 0x8034 r/w interrupt mask register imr enables interrupts on int pin 0x8035 r/w arinc 429 tx ready int enable atrie enables arinc 429 tx ready interrupts fast access registers * register is cleared when read (auto clear) memory mapped register access only holt integrated circuits 8 hi-3210
holt integrated circuits 9 address r/w register mnemonic description 0x805f r/w pins arxbit[7:0] arxbit values of pins arxbit[7:0] 0x8060 r/w pin arxbit0 config reg 1 arx0cr1 arinc 429 bit monitor 0 channel & bit select 0x8061 r/w pin arxbit0 config reg 2 arx0cr2 arinc 429 bit monitor 0 label select 0x8062 r/w pin arxbit1 config reg 1 arx1cr1 arinc 429 bit monitor 1 channel & bit select 0x8063 r/w pin arxbit1 config reg 2 arx1cr2 arinc 429 bit monitor 1 label select 0x8064 r/w pin arxbit2 config reg 1 arx2cr1 arinc 429 bit monitor 2 channel & bit select 0x8065 r/w pin arxbit2 config reg 2 arx2cr2 arinc 429 bit monitor 2 label select 0x8066 r/w pin arxbit3 config reg 1 arx3cr1 arinc 429 bit monitor 3 channel & bit select 0x8067 r/w pin arxbit3 config reg 2 arx3cr2 arinc 429 bit monitor 3 label select 0x8068 r/w pin arxbit4 config reg 1 arx4cr1 arinc 429 bit monitor 4 channel & bit select 0x8069 r/w pin arxbit4 config reg 2 arx4cr2 arinc 429 bit monitor 4 label select 0x806a r/w pin arxbit5 config reg 1 arx5cr1 arinc 429 bit monitor 5 channel & bit select 0x806b r/w pin arxbit5 config reg 2 arx5cr2 arinc 429 bit monitor 5 label select 0x806c r/w pin arxbit6 config reg 1 arx6cr1 arinc 429 bit monitor 6 channel & bit select 0x806d r/w pin arxbit6 config reg 2 arx6cr2 arinc 429 bit monitor 6 label select 0x806e r/w pin arxbit7 config reg 1 arx7cr1 arinc 429 bit monitor 7 channel & bit select 0x806f r/w pin arxbit7 config reg 2 arx7cr2 arinc 429 bit monitor 7 label select 0x8070 r bist control/status bists built-in self-test 0x8071 r bist fail address [7:0] bistfl low-order failing bist memory address 0x8072 r bist fail address [12:8] bistfh high-order failing bist memory address 0x8073 r auto-init fail ls address [7:0] aifl auto-initialization fail address (low-byte) 0x8074 r auto-init fail ms address [15:8] aifh auto-initialization fail address (high byte) hi-3210
hi-3210 system configuration bit name 7 a429rx 6 a429tx 5- 4 - r/w 3 aflip 2- 1- 0- r/w default description r/w 0 this bit must be set to a ?1? to allow the hi-3210 to receive arinc 429 data on any of the eight channels. if set to a zero, the hi-3210 will not respond to any arinc 429 receive bus, regardless of the state of the arinc 429 receive channel control registers. r/w 0 this bit must be set to a ?1? to allow the hi-3210 to transmit arinc 429 data on any of the four channels. if set to a zero, the hi-3210 will not output arinc 429 data and the arinc 429 transmit sequencers will remain in their reset state. r/w 0 0 r/w 0 when set to a ?1?, this bit switches the bit order of the arinc 429 label byte in both receive and transmit channels. r/w 0 not used r/w 0 not used r/w 0 not used must be ?0? must be ?0? 76543210 msb lsb aflip a429tx a429rx master control register (address 0x800f) starting at memory address 0x8000, the hi-3210 contains a set of registers that are used to configure the device. the user needs only to program the hi-3210 configuration registers to completely define the full system operation. the following registers define the hi-3210 top-level configuration: hi-3210 global configuration the configuration registers are divided into three categories, as follows; 1. hi-3210 global configuration 2. arinc 429 receive channel configuration 3. arinc 429 transmit channel configuration holt integrated circuits 10 hi-3210 00 xxx
bit name 7 ready 6 active 5 safe 4 ram busy r 3 prog 2 autoinit 1- 0- r/w default description r 0 this bit is high, when the ready output pin is high, indicating that the part is able to accept and respond to host cpu spi commands r 0 this bit is high after run is asserted and the hi-3210 is in normal operating mode. r 0 this bit goes high when the part enters safe mode as a result of a built-in self-test fail or auto- initialization fail. 0 this is high during the time the ram integrity check is running and ram is clearing r 0 indicates that the hi-3210 is currently in the eeprom programming cycle. note that ready stays low until the cycle is complete. r 0 the hi-3210 is currently loading internal memory, registers and look-up tables from the auto- initialization eeprom r 0 not used r 0 not used 76543210 msb lsb ram busy prog autoinit safe active ready master status register (address 0x800e) the master status register may be read at any time to determine the current operational state of the hi-3210: hi-3210 operational status information holt integrated circuits 11 hi-3210 xx
arinc 429 receive channel configuration each of the eight possible arinc 429 receive channels is configured using its own control register. register address 0x8010 controls arinc 429 receive channel #0, register address 0x8011 controls channel #1 and so on. arinc 429 receive control registers may be read at any time, but can only be written when the device is in the idle state (run input = ?0?, ready output = ?1?). bit name 7 enable 6/lo 5 parityen 4 decoder r/w 3 sd10 2 sd9 1-0 ffs1:0 r/w default description r/w 0 this bit must be set to a ?1? to enable arinc 429 data reception on this channel. r/w 0 selects the arinc 429 bit rate for the arinc 429 receive channel. a ?0? selects high-speed (100kb/s) and a ?1? selects low-speed (12.5kb/s). r/w 0 when this bit is a one, the 32nd received arinc bit is overwritten with a parity flag. the flag bit is set to a zero when the received arinc word, including its parity bit has an odd number of ones. when parityen is a zero, all 32-bits are received without parity checking. 0 when decoder is a ?1?, bits 9 and 10 of arinc 429 words received on this channel must match the sd9 and sd10 bits in the register. arinc words received that do not match the sd conditions are ignored. r/w 0 if decoder is set to a ?1?, then this bit must match the received arinc word bit 10 for the word to be accepted. r/w 0 if decoder is set to a ?1?, then this bit must match the received arinc word bit 9 for the word to be accepted. r/w 0 ffs1 and ffs0 define when this channel?s fifo flag is set, as shown below. hi 76543210 msb lsb decoder sd10 sd9 ffs1 ffs0 parityen rate enable arinc 429 rx control registe r0-7 (address 0x8010 - 0x8017) arinc 429 receive operation the hi-3210 can receive arinc 429 messages from up to eight arinc 429 receive buses. external analog line receivers handle the physical layer connection 0 0 flag never set 0 1 set flag if fifo not empty bit = ?1? 1 0 set flag if fifo > threshold value 1 1 set flag is fifo full bit ?1? ffs1 ffs0 flag set condition holt integrated circuits 12 hi-3210
arinc 429 received data management the hi-3210 supports eight arinc 429 receive buses using on-chip receivers to handle the protocol validation. the eight arinc 429 rx control registers, arxc0 - 7, define the characteristics of each receive channel. the arinc 429 receive function of the hi-3210 is acti- vated by setting the a429rx bit in the master control register. when an arinc 429 message is received by the hi-3210 on any bus, it is checked for protocol compliance. mes- sages with incorrect encoding are rejected. the hi-3210 contains an 8k byte memory for storing arinc 429 received data. the memory is organized by channel number and arinc 429 label value. four bytes of memory are dedicated to each channel / label to store the 32-word arinc 429 message. a look-up table is used to enable an interrupt on receipt of a new arinc 429 message. look-up table bit positions pre- loaded with a ?1? will cause an interrupt to be generated. when a message is received that triggers an interrupt, that channel?s interrupt bit is set in the arinc 429 receive pending interrupt register. if this bit is unmasked in the arinc 429 receive interrupt mask register, the aint output pin is asserted. the label number of the arinc 429 message causing the interrupt is loaded into that chan- nel?s arinc 429 receive interrupt address register (aiar0 - aiar7). because the arinc receive memory is organized by label value, it is not necessary to store the received label value (first eight bits of the arinc message) in the memory. instead, the first byte is used to store a status byte. the six active bits of the status byte are set to ?1? when a new arinc word is stored in the memory. these bits flag the arinc word as new when the location is interrogated by the host cpu or any of the four arinc 429 transmit schedulers. block 1 channel 0, label 00 block 2 channel 0, label 01 block 3 channel 0, label 02 block 2048 channel 7, label ff status byte arinc data byte 2 arinc data byte 3 arinc data byte 4 arinc 429 received data memory organization 0x0000 0x0000 0x0003 0x0004 0x0007 0x0008 0x000b 0x1ffc 0x1fff 0x0001 0x0002 0x0003 etc. holt integrated circuits 13 hi-3210
bit name 7- 6- 5 newhost 4 - r/w 3 new 2 new 1 new 0 new r/w default description r/w 0 not used r/w 0 not used r/w 0 this bit is set when a new arinc 429 word is received and stored in this block. it is reset when the host cpu executes spi instruction 0xc0 - 0xff to read the block. 0 not used tx3 r/w 0 this bit is set when a new arinc 429 word is received and stored in this block. it is reset when the arinc 429 transmit scheduler #3 reads any bytes from the block. tx2 r/w 0 this bit is set when a new arinc 429 word is received and stored in this block. it is reset when thearinc 429 transmit scheduler #2 reads any bytes from the block. tx1 r/w 0 this bit is set when a new arinc 429 word is received and stored in this block. it is reset when thearinc 429 transmit scheduler #1 reads any bytes from the block. tx0 r/w 0 this bit is set when a new arinc 429 word is received and stored in this block. it is reset when the arinc 429 transmit scheduler #0 reads any bytes from the block. 76543210 msb lsb newtx3 newtx2 newtx1 newtx0 newhost status byte arinc 429 received data status byte definition arinc 429 received data interrupt look-up table interrupt look-up table channel 0 interrupt look-up table channel 1 interrupt look-up table channel 7 76543210 0x7b00 0x7b1f 0x7b20 0x7b3f 0x7be0 0x7bff label = 0x00 label = 0x01 label = 0x07 label = 0x08 label = 0x0f label = 0xff label = 0xf8 holt integrated circuits 14 hi-3210 xx x
arinc 429 received data log fifo a 1k x 8 block of memory located between 0x3000 and 0x33ff is reserved for a set of eight arinc 429 received data fifos. there is one fifo for each arinc 429 received data channel. each fifo can hold up to 32 arinc 429 32-bit messages. a look-up table driven filter defines which arinc 429 messages are stored in each fifo. the look-up table is pre-loaded with a ?1? for each bit position corresponding to a selected channel / label combination. the look-up table is located at memory address 0x7a00. when a new arinc 429 message is received that meets the programmed conditions for acceptance (enable look- up table bit = ?1?), it is written into the channel?s receive data fifo. the contents of the fifo may be read by the host cpu using dedicated fifo read spi instructions. the status of each channel?s fifos is monitored by three fifo status registers: fifo not empty, fifo threshold, and fifo full. one bit of each register reflects the current status of each fifo. the fifos are empty following reset. all three status registers are cleared. when an arinc 429 message is written to a fifo, its fifo not empty bit is set to a ?1?. when the fifo contains more than the user-defined number of messages as programmed in the arinc fifo threshold value register, its fifo threshold bit is set. if the fifo is allowed to accumulate 32 messages, its fifo full bit is set. once a fifo is full, subsequent messages continue to be written to the fifo, and the oldest message is lost. the user may generate an interrupt by enabling one of the three fifo status register bits to assert the flag bit in the pending interrupt register. arinc 429 control register bits 1:0 select the condition to trigger the flag interrupt. the fifo feature is particularly useful if the application wishes to accumulate sequential arinc 429 messages of the same label value before reading them. the regular arinc 429 receive data memory will, of course, overwrite messages of the same label value if a new message is received before the host cpu extracts the data. arinc 429 received data fifo (x8) data read by host cpu spi instruction arinc 429 received message message 1 (32-bits) message 2 (32-bits) 0 - 32 messages (32-bits) a fnen afhfn a ffn select flagn fifo not empty fifo threshold fifo full arxcn <1:0> or pir flag } from other channels arinc 429 received data enable look-up table filter look-up table channel 0 filter-look-up table channel 1 filter look-up table channel 7 76543210 0x7a00 0x7a1f 0x7a20 0x7a3f 0x7ae0 0x7aff label = 0x00 label = 0x01 label = 0x07 label = 0x08 label = 0x0f label = 0xff label = 0xf8 holt integrated circuits 15 hi-3210
bit name 7 afne7 6 afne6 5 afne5 4 afne4 r 3 afne3 2 afne2 1 afne 0 afne r/w default description r 0 this bit is set to ?1? if fifo #7 contains at least one arinc 429 message r 0 this bit is set to ?1? if fifo #6 contains at least one arinc 429 message r 0 this bit is set to ?1? if fifo #5 contains at least one arinc 429 message 0 this bit is set to ?1? if fifo #4 contains at least one arinc 429 message r 0 this bit is set to ?1? if fifo #3 contains at least one arinc 429 message r 0 this bit is set to ?1? if fifo #2 contains at least one arinc 429 message 1 r 0 this bit is set to ?1? if fifo #1 contains at least one arinc 429 message 0 r 0 this bit is set to ?1? if fifo #0 contains at least one arinc 429 message 76543210 msb lsb afne4 afne3 afne2 afne1 afne0 afne5 afne6 afne7 fifo not empty register (address 0x802b) arinc 429 received data fifo status registers bit name 7 aftf7 6 aftf6 5 aftf5 4 aftf4 r 3 aftf3 2 aftf2 1 aftf 0 aftf r/w default description r 0 this bit is set to ?1? if fifo #7 contains > threshold number of arinc 429 messages r 0 this bit is set to ?1? if fifo #6 contains > threshold number of arinc 429 messages r 0 this bit is set to ?1? if fifo #5 contains > threshold number of arinc 429 messages 0 this bit is set to ?1? if fifo #4 contains > threshold number of arinc 429 messages r 0 this bit is set to ?1? if fifo #3 contains > threshold number of arinc 429 messages r 0 this bit is set to ?1? if fifo #2 contains > threshold number of arinc 429 messages 1 r 0 this bit is set to ?1? if fifo #1 contains > threshold number of arinc 429 messages 0 r 0 this bit is set to ?1? if fifo #0 contains > threshold number of arinc 429 messages 76543210 msb lsb aftf4 aftf3 aftf2 aftf1 aftf0 aftf5 aftf6 aftf7 fifo threshold register (address 0x802a) bit name 7 afff7 6 afff6 5 afff5 4 afff4 r/w 3 afff3 2 afff2 1 afff 0 afff r/w default description r/w 0 this bit is set to ?1? if fifo #7 contains 32 arinc 429 messages r/w 0 this bit is set to ?1? if fifo #6 contains 32 arinc 429 messages r/w 0 this bit is set to ?1? if fifo #5 contains 32 arinc 429 messages 0 this bit is set to ?1? if fifo #4 contains 32 arinc 429 messages r/w 0 this bit is set to ?1? if fifo #3 contains 32 arinc 429 messages r/w 0 this bit is set to ?1? if fifo #2 contains 32 arinc 429 messages 1 r/w 0 this bit is set to ?1? if fifo #1 contains 32 arinc 429 messages 0 r/w 0 this bit is set to ?1? if fifo #0 contains 32 arinc 429 messages 76543210 msb lsb afff4 afff3 afff2 afff1 afff0 afff5 afff6 afff7 fifo full register (address 0x8029) holt integrated circuits 16 hi-3210
threshold value description 00000 threshold flag is set if at least 1 message is in fifo (same as fifo not empty flag) 00001 threshold flag is set if more than one message are in the fifo 00010 threshold flag is set if more than two messages are in the fifo 00011 threshold flag is set if more than three messages are in the fifo 10000 threshold flag is set if more than sixteen messages are in the fifo (default) 11111 threshold flag is set if 32 messages are in the fifo (same as fifo full flag) 76543210 msb lsb fifo threshold value (address 0x8021) arinc 429 fifo threshold value register threshold 000 arinc 429 loop-back self-test the hi-3210 includes an arinc 429 loop-back feature, which allows users to exercise the arinc 429 transmit and receive channels for self-test purposes. the arinc 429 loop-back register, aloop defines which receiver channels are in loop-back mode. when a ?1? is programmed in the aloop bit position for a receiver, then its arinc 429 bus connection to the external pins is broken and instead the input is connected to one of the four arinc 429 transmit channels. transmit channel 0 is connected to receive channel 0 and 1, transmit channel 1 is connected to receive channels 2 and 3, and so on. when in loop-back mode, incoming arinc 429 messages are ignored by the hi-3210. when running in loop-back mode the arinc 429 transmit pins may be disabled by pulling the txmsk input high. this prevents test messages from being output to the external arinc 429 transmit buses. bit name 7 aloop7 6a 6 5a 5 4 a 4 r/w 3a 3 2a 2 1a 0a r/w default description r/w 0 this bit is set to ?1? to loop-back transmit channel 3 to receiver 7 loop r/w 0 this bit is set to ?1? to loop-back transmit channel 3 to receiver 6 loop r/w 0 this bit is set to ?1? to loop-back transmit channel 2 to receiver 5 loop 0 this bit is set to ?1? to loop-back transmit channel 2 to receiver 4 loop r/w 0 this bit is set to ?1? to loop-back transmit channel 1 to receiver 3 loop r/w 0 this bit is set to ?1? to loop-back transmit channel 1 to receiver 2 loop1 r/w 0 this bit is set to ?1? to loop-back transmit channel 0 to receiver 1 loop0 r/w 0 this bit is set to ?1? to loop-back transmit channel 0 to receiver 0 76543210 msb lsb aloop4 aloop3 aloop2 aloop1 aloop0 aloop5 aloop6 aloop7 arinc 429 loopback (address 0x8022) holt integrated circuits 17 default = 0x10 hi-3210
arinc 429 bit ordering arinc 429 messages consist of a 32-bit sequence as shown below. the first eight bits that appear on the arinc 429 bus are the label byte. the next twenty three bits comprise a data field which presents data in a variety of formats defined in the arinc 429 specification. the last bit transmitted is an odd parity bit. the hi-3210 stores the received message as four bytes. the bytes are stored in memory in little-endian order. that is to say, the label byte (or status byte) is stored at the lowest memory address, the byte representing received bits 9 through 16 is stored at the next address, the byte representing bits 17 through 24 at the next address and the byte representing bits 25 though 32 at the highest address. the arinc 429 specifies the msb of the label as arinc bit 1. conversely, the data field msb is bit 31. so the bit significance of the label byte and data fields are opposite. the hi-3210 may be programmed to ?flip? the bit ordering of the label byte as soon as it is received and immediately prior to transmission. this is accomplished by setting the aflip bit to a ?1? in the master control register. note that once the label byte has been flipped, the hi-3210 handles the flipped data byte ?post-flip? for the purpose of label interrupt matching, filtering and storage. 7 6 5 4 3 2 1 8 lsb arinc 429 message as received / transmitted on the arinc 429 serial bus 910 11 12 13 14 15 16 sdi sdi 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 parity label data msb lsb msb time 7 6 5 4 3 2 1 8 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 76 5 4 3 21 8 arinc 429 message as stored in hi-3210 memory byte 0 byte 1 byte 2 byte 3 aflip = ?0? aflip = ?1? 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 holt integrated circuits 18 hi-3200, hi-3201
holt integrated circuits 19 arinc 429 bit monitor pins 76543210 msb lsb arxbit4 arxbit3 arxbit2 arxbit1 arxbit0 arxbit5 arxbit6 arxbit7 pins arxbit[7:0] register (address 0x805f) bit name 7:0 arxbit[7:0] r/w default description r/w 0 these bits reflect the value of the corresponding pins arxbit[7:0]. after reset, all values are zero. when a monitored arinc 429 bit changes, this register is updated with the value, which is reflected on the corresponding pin. the purpose of this register is to allow the user to preset the arxbit values after chip reset. 76543210 msb lsb arxcr14 arxcr13 arxcr12 arxcr11 arxcr10 arxcr15 arxcr16 arxcr17 pin arxbit0 configuration register 1 (address 0x8060) bit name 7:5 arxcr1[7:5] r/w default description r/w 0 these bits select which receive channel (0 through 7) will have bits monitored and reflected on the pin arxbit0. 4:0 arxcr1[4:0] r/w 0 these bits select which bit (8 through 31) of the arinc payload will be reflected on the pin arxbit0. the receiver is specified by bits arx0cr1[7:5] and the target label is specified by pin arxbit0 configuration register 2 described below. note that bits 0 through 7 of the arinc payload are not monitored and selecting these bits results in no effect. 76543210 msb lsb arxcr24 arxcr23 arxcr22 arxcr21 arxcr20 arxcr25 arxcr26 arxcr27 pin arxbit0 configuration register 2 (address 0x8061) bit name 7:0 arxcr2[7:0] r/w default description r/w 0 these bits select which label (0 through 255) will have bits monitored and reflected on the pin arxbit0. the receive channel and specific bits monitored are specified in arxbit0 configuration register 1 described above. each pin arxbit1 through arxbit7 are also specified by a pair of configuration registers similar to arxbit0 described above. functionality is exactly the same. the register addresses for each pin specification are listed in the register map section (see page 9). note that hi-3210 provides external monitoring of eight bits through pins arxbit7 to arxbit0. pins arxbit1 through arxbit7 configuration registers (addresses 0x8062 to 0x806f) hi-3210 the hi-3210 has the capability of externally monitoring any arinc 429 received payload bit through the pins arxbit[7:0]. when the appropriate arinc 429 receiver is enabled and the target label is received, the monitored bit value will be reflected on the pin. this allows the user to monitor any arinc 429 received payload bit without performing any host spi reads. the following registers configure the functionality of these monitor pins. note that all these control register bits are reset to zero.
arinc 429 transmit channel configuration each of the four available arinc 429 transmit channels is configured using its own register. register address 0x8018 controls arinc 429 transmit channel #0, register address 0x8019 controls channel #1 and so on. the atxcn registers may be written or read at any time. arinc 429 tx control registe r0-3 (address 0x8018 - 0x801b) 76543210 msb lsb even / odd skip parity / data hi / lo run / stop bit name 7 run / 6/lo 5 parity / 4 even / r/w 3 skip 2- 1- 0- r/w default description stop hi data odd r/w 0 when zero, transmission from this arinc 429 transmit channel is suspended after the currently transmitting label is sent. when this bit is taken high, transmission starts at the beginning of the descriptor table for this channel. r/w 0 selects the transmission rate for the arinc 429 transmit channel. a ?0? selects high-speed (100kb/s) and a ?1? selects low-speed (12.5kb/s). r/w 0 when this bit is a one, the 32nd transmitted arinc bit is overwritten with a parity flag. when this bit is a zero, all 32-bits are transmitted as data. 0 when parity / data is a ?1?, this bit defines whether th 32nd transmitted bit is set for even or odd parity. a ?1? selects even parity and a ?0? selects odd parity. r/w 0 when set a ?1? instructs the transmit sequencer to wait for the next repetition rate counter rollover before beginning a new transmission cycle. a ?0? causes an immediate restart of the cycle following completion of the prior cycle. r/w 0 not used r/w 0 not used r/w 0 not used arinc 429 transmit operation the hi-3210 has four on-board arinc 429 transmit channels which directly drive arinc 429 differential line drivers such as the holt hi-8596. arinc 429 words may be written to the transmitters either directly, using an spi instruction, or be generated automatically using the four arinc 429 message schedulers. holt integrated circuits 20 hi-3210 xxx
arinc 429 transmit scheduler each of the four arinc 429 transmit channels has its own transmit controller. the controller is user- programmed to output arinc labels in a predefined order and repetition rate. a sequence of up to 256 arinc labels may be transmitted before repeating the sequence. a descriptor table with up to 256 entries (descriptors) is compiled by the user to define the sequence of arinc 429 messages transmitted on each channel. when the run/ bit in the arinc tx control register is asserted, the controller compiles the first 32-bit arinc word from the instructions given by the first descriptor and then transmits it. a transmit sequence pointer then increments to the next descriptor in the table and the process is repeated for descriptor number 2. arinc 429 messages continue to be compiled and transmitted until the last descriptor in the table. the end of the table is marked by a special descriptor if not all 256 entries are needed. the sequence pointer is then reset to zero. a repetition rate counter is used to time the start of the next transmission cycle. stop the user is responsible for construction of the descriptor table and for setting the repetition rate prior to asserting run/stop. facilities exist for immediate cycle repetition and for single-cycle operation. the byte content of each arinc 429 message transmitted is user defined by the descriptor contents. data bytes may be sourced from the host cpu / auto- initialization eeprom (immediate data) or from the arinc 429 receive memory (arinc indexed). this allows received arinc data to be re-transmitted on another bus with or without filtering, label byte re- assignment or data modification. it also allows data from multiple arinc 429 receive buses to be re-packetized into new arinc 429 transmitted messages. conditional transmission control allows sequenced words to be skipped if no new data is available. each arinc 429 transmit channel is independently configured with its own arinc 429 tx control register, atxcr0-3, as previously described. sequence 0 descriptor frame 0x4000 action byte 1 repetion rate register repetition rate counter sequence pointer 000 sequence 1 descriptor frame sequence 2 descriptor frame sequence 3 descriptor frame sequence 4 descriptor frame sequence 5 descriptor frame sequence 254 descriptor frame sequence 255 descriptor frame value byte 1 action byte 2 action byte 3 action byte 4 value byte 2 value byte 3 value byte 4 arinc 429 transmit descriptor table 0x4008 0x4010 0x4018 0x4020 0x4028 0x47f0 0x47f8 0x47ff (memory addresses shown for arinc tx channel 0) the value of each arinc 429 label transmitted in the sequence is defined by its eight-byte descriptor. the descriptor consists of one ?action byte? and one ?value? byte for each of the four bytes that make up the arinc 429 transmitted label. the four pairs of action and value bytes describe where the data for each byte may be found. different op-codes allow the data source to be host cpu populated fixed values, or values from specific locations within the arinc 429 receive memory. action byte 1 also has one additional op-code to facilitate sequence flow control. the construction of action and value bytes are described in the next section. holt integrated circuits 21 hi-3210
76543210 msb lsb transmit sequence pointers 0 -3 (address 0x802c - 0x802f) current sequence number 76543210 msb lsb repetition rate register (address 0x801c - 0x801f) channel repetition period the transmit sequence pointer is set to zero on master reset. once the control register run / bit goes high, sequence execution begins at sequence count zero. after the first word is sent, the pointer is incremented by one descriptor (counts descriptor frames). stop this continues until the programmed sequence is complete. the sequence pointer is then reset to the beginning of the descriptor table and program execution begins as soon the channel repetition rate counter time elapses. the repetition rate register value defines the time interval between successive starts of the programmed transmit sequence for each arinc 429 transmit channel. the value is set in binary, with the lsb representing 10 ms. repetition rate time periods may therefore be set from 0 ms to 2.55 seconds if the repetition rate is shorter than the minimum time needed to transmit all arinc 429 words in the sequence (but not zero), the transmit sequence will begin again immediately if the control register skip bit is a zero. if the skip bit is a one, the sequencer will wait until the next rollover of the repetition rate counter before starting a new cycle. when the repetition rate counter is programmed to zero (default), the transmit sequence shall execute one time only. a zero - to - one transition of the run/stop bit will cause the transmit sequence to start. one-time execution of the sequencer is useful when transmitting arinc 429 words directly from the host cpu. one or more immediate-mode descriptors can be written into the sequence table, transmitted, and then refreshed for the next cycle. holt integrated circuits 22 hi-3210
arinc 429 byte 1 descriptor 76543210 msb lsb index index value op-code description 000 xxxxx xxxxxxxx end of sequence. when op-code 000 is encountered by the sequencer before it reaches sequence number 255, the sequencer resets to zero and begins the next transmission cycle starting at descriptor number 0 as soon as the repitition rate counter rolls over. note that the descriptor table is cleared following master reset, so no arinc 429 transmissions are possible until the sequence table has been configured. 001 xxxxx xxxxxxxx no-operation. this descriptor is ignored and the sequencer increments to the next descriptor in the sequence. this opcode may be used to temporarily suspend transmission of a particular message in the sequence, without having to modify the remaining bit fields of the descriptor or reloading the entire descriptor block in order to delete the entry. 010 xxxxx llllllll immediate data. the value contained in the descriptor value data byte is loaded into byte 1 (the arinc 429 ?label? byte) of the arinc 429 label to be transmitted. 011 cccxx llllllll immediate data conditional. the newtxn bit corresponding to the arinc data ram location defined by channel ?ccc? and label block ?llllllll? is read. llllllll is used as byte 1 if newtxn is set for this within this descriptor frame. if newtxn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. the newtxn bit for the referenced arinc ram block is reset. 100 cccbb llllllll indexed data. the value of arinc data ram location defined by channel ?ccc?, label block ?llllllll? and byte number ?bb? is loaded into byte 1 of the arinc 429 label to be transmitted. 101 cccbb llllllll indexed data conditional. the newtxn bit corresponding to the arinc data ram location defined by channel ?ccc?, label block ?llllllll? and byte number ?bb? is read. the corresponding byte is used as byte 1 if newtxn is set for this within this descriptor frame. if newtxn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. the newtxn bit for the referenced arinc ram block is reset. 110 xxxx xxxxxxxx reserved. do not use. 111 xxxx xxxxxxxx reserved. do not use. or any other conditional opcode or any other conditional opcode 76543210 msb lsb value op-code action byte value byte holt integrated circuits 23 hi-3210
index value 000 op-code description xxxxx xxxxxxxx no-op op-code. arinc 429 word construction will be terminated and the sequencer will move on to the next descriptor in the table. 001 xxxxx xxxxxxxx no-op op-code. arinc 429 word construction will be terminated and the sequencer will move on to the next descriptor in the table. 010 xxxxx llllllll immediate data. the value contained in the descriptor value data byte is loaded into this byte position of the arinc 429 32-bit message to be transmitted. 011 cccxx llllllll immediate data conditional. the newtxn bit corresponding to the arinc data ram location defined by channel ?ccc? and label block ?llllllll? is read. llllllll is used if newtxn is set for this within this descriptor frame. if newtxn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. the newtxn bit for the referenced arinc ram block is reset. 100 cccbb llllllll indexed data. the value of arinc data ram location defined by channel ?ccc?, label block ?llllllll? and byte number ?bb? is loaded into this byte position of the arinc 429 label to be transmitted. 101 cccbb llllllll indexed data conditional. the newtxn bit corresponding to the arinc data ram location defined by channel ?ccc?, label block ?llllllll? and byte number ?bb? is read. the corresponding byte is used if newtxn is set for this within this descriptor frame. if newtxn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. the newtxn bit for the referenced arinc ram block is reset. 110 xxxx xxxxxxxx reserved. do not use. 111 xxxx xxxxxxxx reserved. do not use. or any other conditional opcode or any other conditional opcode arinc 429 byte s2-4 descriptor 76543210 msb lsb index 76543210 msb lsb value op-code action byte value byte holt integrated circuits 24 hi-3210
arinc 429 immediate transmit option the host cpu may instruct the hi-3210 to transmit an arinc 429 message immediately using a special spi command. the spi command selects the transmit channel and provides the four bytes of data to be sent as a 32-bit arinc 429 message. if the transmit channel?s sequencer is not running (atcr bit run/ = ?0?), or the sequencer is waiting for the repetition rate counter to rollover, then the new arinc 429 message is transmitted without delay. stop if the transmit sequencer for the selected channel is active, then the new message is transmitted as soon as the current message has been sent. the sequencer then resumes operation at the next location in the queue. both the run input and the master control register a429tx bit must be high to enable any arinc 429 transmission. table 1 lists the host cpu spi instruction format. holt integrated circuits 25 hi-3210
after power-on, the hi-3210 is in an undefined state. the reset pin must be taken high to begin device initialization. the reset pin may be asserted at any time. taking reset high immediately stops all execution and sets the ready output low indicating that the part is in the reset state. on the falling edge of reset, the hi-3210 samples the state of the mode2-0 input pins. this is the only occasion these inputs are sampled. the state of the mode pins determines one of six possible initialization sequences as shown in the following diagram. these six initialization modes allow the user to customize the start- up configuration of the device. once the initialization is complete, the device enters the idle state when the ready pin goes high. in idle state, the host cpu may communicate with the hi-3210 memory and registers using the host cpu spi link. when in the idle state, the hi-3210 does not transmit or receive any messages on any of the arinc 429 buses. to begin data bus operation, the user must transition the run input from a low to high state. immediately following the rising edge of run, the part enters the active state and bus message processing begins. during initialization, various device configuration tasks are performed according to the mode selection set at the mode2:0 input pins. the available options are: he part enters the ?safe? state, in which the hi-3210 is able to accept and respond to host cpu spi instructions, but cannot enter normal operating mode until the reset input is taken high to repeat the initialization sequence. in modes 0, 1, 2, 3 and 5, the hi-3210 automatically clears all memory locations in the address range 0x0000 to 0x33ff. this is the space reserved for arinc 429 message data. configuration tables and hi-3210 registers are not affected. 1. ram integrity check 2. clear data memory in modes 2 and 3, the hi-3210 performs a ram integrity check. a read/write check is performed on the entire ram space. an incrementing pattern is written to sequential ram locations then this pattern is read and verified. each ram location is re-written with the 1s complement of its current contents then this pattern is read and verified. the incrementing pattern followed by its 1s complement ensures that each ram location can store bot h a 1 and 0 state. if the ram integrity check fails, the mint pin is asserted and the pending interrupt register ramfail bit is set. t the ramfail interrupt is not maskable. 3. initialize registers and clear all memory 4. auto-initialize from eeprom in addition to clearing data memory (0x0000 to 0x33ff), modes 0, 1, 2, and 3 also clear all configuration and look- up tables (0x3400 to 0x7fff) as well as setting all registers (0x8000 to 0x807f) to their default states. all registers default to zero unless otherwise noted. the contents of the auto-initialization eeprom are copied into the hi-3210 memory and registers via the eeprom spi interface. the part verifies the integrity of the data transfer from the eeprom by running through a byte-by-byte compare routine and a checksum validation. once initialization is complete, the part enters the idle state. the host cpu may read and write hi-3210 internal memory and registers in all modes. if not using the auto- initizarion feature, the host cpu should configure the device at this time. modes 6 and 7 are reserved and should not be used. note: if a compare error is detected, the autoerr bit is set in the pending interrupt register, the mint output is asserted, the location of the error is captured in the auto-init fail address registers 0x8073 (auto-init fail ls address) and 0x8074 (auto-init fail ms address) and the part enters the safe state. if a checksum error is detected, the chkerr bit is set in the pending interrupt register, the mint output is asserted and the part enters the safe state. the autoerr and the chkerr interrupts are not maskable. holt integrated circuits 26 hi-3210 reset and start-up operation
reset and start-up operation reset driven to ?1? stop execution, ready => 0 reset driven to ?0? sample mode2:0 inputs ram pass ? copy ok ? set autoerror int = 1 safe state set ramfail int = 1 no yes no yes reset state mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 perform ram integrity check no no yes yes no no reserved reserved clear data memory yes yes yes yes no yes reserved reserved (0x0000 - 0x33ff) initialize registers and yes yes yes yes no no reserved reserved clear configuration tables (0x3400 - 0xffff) auto-initialize from no yes no yes no no reserved reserved eeprom ready => 1 run drive n0-1 idle state active state holt integrated circuits 27 hi-3210
interrupt handling the hi-3210 includes a simple, user-selectable interrupt handler. two types of interrupt are possible - message event driven (arinc 429 bus), and fault driven. as described earlier, the user can elect to generate an interrupt upon receipt of an arinc 429 message on any combination of the eight available channels and for any of the possible 256 label byte (arinc message bits 1-8) values. interrupts are enabled when the arinc 429 rx interrupt look-up bit is a ?1?. when a message arrives that is flagged to generate an interrupt, that channel?s bit is set in the arinc 429 receiver pending interrupt register apir. the arinc 429 interrupt address register (aiar) for that channel is updated with the arinc 429 8-bit label value. for example, if arinc receive channel 7 is enabled for interrupts when messages with arinc label 0xd4 arrive, then on receipt of such a message, apir bit 7 is set to a ?1? and the value 0xd4 is written to aiar7. if the corresponding bit in the arinc 429 receive interrupt mask register is a ?1? the aint interrupt output will go high and stay high until the aack input pin is driven high. driving aack high, causes the aint pin to return to zero. a special indexed spi read instruction is available to allow the host to efficiently retrieve arinc 429 messages which have interrupts enabled (see spi instruction set section). note that if aack is tied high permanently, the aint pin will go high for approximately 1 us before returning to zero. a host cpu read of the apir register reads the current value and resets apir to 0x00. arinc 429 receive interrupts fault interrupts there are four fault interrupt bits in the pir. fault interrupts are not maskable, and their interrupt mask bits are fixed at a ?1?. copyerr is set when the hi-3210 detects a mismatch between ram and eeprom after attempting to program the auto-initialization eeprom. autoerr is set when the auto-initialization eeprom read verification cycle detects a mismatch between the on-chip memory and eeprom following auto- initialization. chkerr is set when an auto-initialization checksum error is detected. the ramfail bit is set if the built-in self test sequence fails. holt integrated circuits 28 hi-3210
bit name 3 flag 0 - r/w r/w default description 7 copyerr r 1 copyerr is not maskable 6 autoerr r 1 autoerr is not maskable 5 chkerr r 1 chkerr is not maskable 4 ramfail r 1 ramfail is not maskable r/w 0 int is asserted if this bit is a ?1? and the pir flag bit is set 2 atxrdy r/w 0 int is asserted if this bit is a ?1? and the pir atxrdy bit is set 1 - r/w 0 not used 0 not used 76543210 msb lsb bistfail flag atxrdy chkerr autoerr copyerr interrupt register mask register (address 0x8034) bit name 3 flag 1- 0 - r/w r/w default description 7 copyerr r/w 0 ee copy error. ram - eeprom mismatch 6 autoerr r/w 0 auto-inititailization ram read error 5 chkerr r/w 0 auto-initialization checksum fail 4 ramfail r/w 0 power-on reset ram integrity check fail r/w 0 logical or of arinc 429 receive fifo flag signals 2 atxrdy r/w 0 arinc 429 host tx ready. used with host spi op-code 100101tt (see table 1). interrupt when ready for next 32-bit word from host r/w 0 not used 0 not used 76543210 msb lsb bistfail flag atxrdy chkerr autoerr copyerr pending interrupt register (address 0x800a) holt integrated circuits 29 hi-3210 xx xx
holt integrated circuits 30 hi-3210 ram built-in self-test the hi-3210 offers a built-in self-test (bist) feature which can be used to check ram integrity. the bist control/status register is used to control the bist function. all tests are destructive, overwriting data present before test commencement. 76543210 msb lsb rbsel0 rbstart rbfail rbpass rbsel1 rbsel2 rbfail bist control/status register (address 0x8070) this register controls ram built-in self-test. bits 0,1 are read only. the remaining bits in this register are read-write but can be written only in mode2:0 = 0x04. bist control register bits provide a means for the host to perform ram self-test at other times. register bits 6:4 select ram test type. then bit 3 starts the selected ram test, and bits 1:0 report a fail/pass result after test completion. 7 rbffail ram bist force failure. when this bit is asserted, ram test failure is forced to verify that ram bist logic is functional. 6:4 rbsel2-0 ram bist select bits 2-0. this 3-bit field selects the ram bist test mode applied when the rbstart bit is set: 000 idle 001 pattern test, described below 010 write 0x00 to ram address range 0x0000 - 0x7fff 011 read and verify 0x00 over ram address range 0x0000 - 0x7fff 100 write 0xff to ram address range 0x0000 - 0x7fff 101 read and verify 0xff over ram address range 0x0000 - 0x7fff 110 inc / dec test performs only step s5-8ofthe pattern test below 111 idle 1. write 0x00 to all ram locations, 0x0000 through 0x7fff 2. repeat the following sequence for each ram location from 0x0000 through 0x7fff: a. read and verify 0x00 b. write then read and verify 0x55 c. write then read and verify 0xaa d. write then read and verify 0x33 e. write then read and verify 0xcc f. write then read and verify 0x0f g. write then read and verify 0xf0 h. write then read and verify 0x00 i. write then read and verify 0xff j. write 0x00 then increment ram address and go to step (a) 3. write 0xff to all ram locations, 0x0000 through 0x7fff 4. repeat the following sequence for each ram location from 0x0000 through 0x7fff: a. read and verify 0xff b. write then read and verify 0x55 c. write then read and verify 0xaa d. write then read and verify 0x33 e. write then read and verify 0xcc bit no. mnemonic interrupt type rbsel2:0 selected ram test description of the ram bist ?pattern? test selected when register bits rbsel2:0 = 001: x
holt integrated circuits 31 hi-3210 f. write then read and verify 0x0f g. write then read and verify 0xf0 h. write then read and verify 0x00 i. write then read and verify 0xff j. write 0xff then increment ram address and go to step (a) 5. write an incrementing pattern into sequential ram locations from 0x0000 to 0x7fff 6. read each memory location from 0x0000 to 0x7fff and verify the contents 7. write 1s complement of each cell?s current contents, into each ram location (same addr range) 8. read each memory location and verify the contents 3 rbstrt ram bist start. writing logic 1 to this bit initiates the ram bist test selected by register bits rbsel2:0. the rbstrt bit can only be set in mode2:0 = 0x04. this bit is automatically cleared upon test completion. register bits 1:0 indicate fail / pass test result. 2 --------- not used. 1 rbfail ram bist fail. device logic asserts this bit when failure occurs while performing the selected ram test. this bit is automatically cleared when rbstrt bit 3 is set. when bist failure occurs, a clue to the failing ram address can be read at register addresses 0x8071 and 0x8072. for speed, the ram bist concurrently tests four consecutive ram addresses in parallel. if a test failure occurs, register addresses 0x8071 and 0x8072 can be used to determine the four ram addresses tested. 0 rbpass ram bist pass. device logic asserts this bit when the selected ram test completes without error. this bit is automatically cleared when rbstrt bit 3 is set. 76543210 msb lsb lower bist fail address register (address 0x8071) bistfl 13 12 11 10 9 8 msb lsb upper bist fail address register (address 0x8072) bistfh 15 14 xx
in the hi-3210, internal ram and registers occupy a (32k + 128) x 8 address space. the lowest 32k addresses access ram locations and the remaining addresses access registers. timing is identical for register operations and ram operations via the serial peripheral interface, and read and write operations have likewise identical timing. host access is only allowed when the part is ready or in safe mode. writes will be blocked and reads will return the master status register value until either of these modes occur. cpol- cpha a rising edge on chip select terminates the serial transfer and reinitializes the hi-3210 spi for the next transfer. if goes high before a full byte is clocked by sck, the incomplete byte clocked into the device si pin is discarded. in the general case, both master and slave simultaneously send and receive serial data (full duplex) as shown in figure 1 below. when the hi-3210 is sending data on so during read operations, activity on its si input is ignored. figures 2 and 3 show actual behavior for the hi-3210 so output. note: serial peripheral interface (spi) basics cs cs cs cs the hi-3210 uses an spi synchronous serial interface for host access to registers and ram. host serial communication is enabled through the chip select ( ) pin, and is accessed via a three-wire interface consisting of serial data input (si) from the host, serial data output (so) to the host and serial clock (sck). all programming cycles are completely self-timed, and no erase cycle is required before write. the spi (serial peripheral interface) protocol specifies master and slave operation; the hi-3210 host cpu interface operates as an spi slave. the spi protocol defines two parameters, cpol (clock polarity) and cpha (clock phase). the possible combinations define four possible "spi modes." without describing details of the spi modes, the hi-3210 operates in the two modes where input data for each device ( master and slave) is clocked on the rising edge of sck, and output data for each device changes on the falling edge. these are known as spi mode 0 (cpha = 0, cpol = 0) and spi mode 3 (cpha = 1, cpol = 1). be sure to set the host spi logic for one of these modes. as seen in figure 1, the difference between spi modes 0 and 3 is the idle state for the sck signal. there is no configuration setting in the hi-3210 to select spi mode 0 or mode 3 because compatibility is automatic. beyond this point, the hi-3210 data sheet only shows the spi mode 0 sck signal in timing diagrams. the spi protocol transfers serial data as 8-bit bytes. once chip select is asserted, the next 8 rising edges on sck latch input data into the master and slave devices, starting with each byte?s most-significant bit. the hi-3210 spi can be clocked at 20 mhz. multiple bytes may be transferred when the host holds low after the first byte transferred, and continues to clock sck in multiples of 8 clocks. cs host serial peripheral interface msb lsb msb lsb high z high z 01234567 cs so si sck (spi mode 3) 01234567 sck (spi mode 0) figure 1. generalized single-byte transfer using spi protocol, sck is shown for spi modes 0 and 3 holt integrated circuits 32 hi-3210
figure 2. single-byte read from ram or a register cs so si sck spi mode 0 msb lsb 0 12 3 4 5 67 high z high z 0 12 3 4 5 67 msb lsb msb lsb data byte command byte host may continue to assert here to read sequential byte(s) when allowed by the instruction. each byte needs 8 sck clocks. cs holt integrated circuits 33 figure 3. 2-byte write to ram or a register pair cs so si sck spi mode 0 msb lsb 0 12 3 4 5 67 0 12 3 4 5 670 12 3 4 5 67 msb lsb msb lsb data byte 0 data byte 1 command byte host may continue to assert here to write sequential byte(s) when allowed by the spi instruction. each byte needs 8 sck clocks. cs high z hi-3210
hi-3210 spi commands for the hi-3210, each spi read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion of . since hi-3210 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte. the spi command set includes directly-addressed read and write commands for registers 0 through 15 (memory address 0x8000 to 0x800f). the 8-bit pattern for these commands has the general form 0-w-r-r-r-r-0-0 where rrrr is the 4-bit register number, and w signifies write when 1, or read when 0. figures 2 and 3 show read and write timing as it appears for fast-access register operations. the command byte is immediately followed by a data byte comprising the 8-bit data word read or written. for a single register read or write, is negated after the data byte is transferred. multiple register read or write cycles may be performed by transferring more than one byte before is negated. multiple register access occur in address order starting with the register specified in the spi instruction. note: register locations not shown in table 1 are ?reserved? and cannot be written using any spi command. further, these register addresses will not provide meaningful data in response to read commands. refer to the hi-3210 spi command set shown in table 1. spi commands other than fast-access use an address pointer to indicate the address for read or write transactions. this sixteen-bit memory address pointer (map) must be initialized before any non-fast-access read or write operation. two dedicated spi instructions are used to write and read the map. spi instruction 0x8c followed by two data bytes is used to write map. spi instruction 0x88 reads two data bytes from map. the first byte is the most significant eight bytes of the address. for example, spi sequence 0x8c, 0x12, 0x34 write the value 0x1234 into the map. two spi instructions read and write data bytes to memory or registers using the map as an address pointer. single or multi-byte reads and writes may be performed. map is incremented after each byte access. ; must be negated after the command, then reasserted for the following read or write command. two single-byte spi commands use the current address pointer value in map without first loading or otherwise modifying it: 0x80 read location addressed by pointer value 0x84 write location addressed by pointer value using a single-byte spi command, the address pointer can be directly loaded with the memory address for the last received arinc 429 message which triggered an interrupt. the hi-3210 will retrieve the current arinc receive interrupt vector for a given channel (rrr), calculate the memory address for the first word of the corresponding receive memory data block and write it to the memory address pointer (map). read the location addressed by the new pointer value. this command can be used to read just the most recent arinc 429 receive status byte, or may be used to start a four-byte read because memory pointer auto-increment occurs after the status byte is read. the hi-3210 will retrieve the current arinc receive interrupt vector for a given channel (rrr), calculate the memory address for the first word of the corresponding receive memory data block and write it to the memory address pointer (map). output the value of the receive interrupt vector (arinc 429 label byte). this command can be used to read just the most recent arinc 429 label value received, or may be used to start a four-byte read to output the entire four-byte arinc cs cs cs cs fast access commands for registers 0-15 ram and register indirect addressing two command bytes cannot be ?chained? command read operation command write operation op code 110rrr00 op code 111rrr00 note: when the primary or fast-access address pointer is used for auto-incrementing multi-word read/write and reaches the top of the memory address range (0x7fff), or the top of the register address range (0xffff) attempts to read further bytes will result the terminal address (0x7fff or 0xffff) being output again. the host should avoid this situation. either of these commands can be used to read or write a single location, or may be used when starting a multi-byte read or write by using the pointer?s auto-increment feature. several other hi-3210 spi commands load or otherwise modify the memory address pointer before initiating a read or write process. these commands are designed to allow speedy access to messages received on the arinc 429 buses. special purpose commands holt integrated circuits 34 hi-3210
message, because memory pointer auto-increment occurs after the label byte is output. writes an arinc 429 message to arinc 429 transmit scheduler tt for immediate transmission, where tt represents the channel number. op code 100101tt table 1. defined instructions description fast register read from register rrrr fast register write to register rrrr read memory at address map write memory at address map read arinc block at receive channel rrr, label read read map write map transmit arinc 429 message on transmit bus tt read arinc 429 fifo # rrr. reads exactly four bytes arinc message at receive channel rrr, label auto increment yes yes yes yes no yes no no no no op code hex 0x00 - 0x3c 0x40 - 0x7c 0x80 0x84 0xa0 - 0xbc 0xc0 - 0xdc 0xe0 - 0xfc 0x88 0x8c 0x94 - 0x97 op code binary 00rrrr00 01rrrr00 110rrr00 111rrr00 10000000 10000100 10001000 10001100 100101tt 101rrr00 number of data bytes 1++ 1++ 1++ 1++ 2 2 4 4, 8, 12... 4 4 command bits hex fast-access 76543210 byte write 01000000 0x40 n/a (read only) 01000100 0x44 n/a (read only) 01001000 0x48 n/a (read only) 01001100 0x4c n/a (read only) 01010000 0x50 n/a (read only) 01010100 0x54 n/a (read only) 01011000 0x58 n/a (read only) 01011100 0x5c n/a (read only) 01100000 0x60 n/a (read only) 01100100 0x64 reserved 01101000 0x68 n/a (read only) 01101100 0x6c reserved 01110000 0x70 n/a (read only) 01110100 0x74 n/a (read only) 01111000 0x78 n/a (read only) 01111100 0x7c write mcr command bits hex fast-access 76543210 byte read 00000000 0x00 read apir 00000100 0x04 read aiar0 00001000 0x08 read aiar1 00001100 0x0c read aiar2 00010000 0x10 read aiar3 00010100 0x14 read aiar4 00011000 0x18 read aiar5 00011100 0x1c read aiar6 00100000 0x20 read aiar7 00100100 0x24 reserved 00101000 0x28 read pir 00101100 0x2c reserved 00110000 0x30 read amff 00110100 0x34 read atrb 00111000 0x38 read msr 00111100 0x3c read mcr fast-access spi commands for registers 0-15 command bits 5:2 convey the 4-bit register address holt integrated circuits 35 hi-3210
following reset, the hi-3210 may be completely configured by automatically copying the contents of an external eeprom into hi-3210 memory and registers. an spi enabled 64kbyte eeprom is used for this purpose. the eeprom memory space is mapped to the hi-3210 as shown in the diagram below. all configuration memory blocks are copied. the arinc 429 received data memory contents and arinc 429 receive log fifo contents are not copied to or from the eeprom. the hi-3210 can be used to program the auto-initialization eeprom. when the hi-3210 is in its idle state (run input = ?0?), a three step sequence must be performed to begin the eeprom programming cycle: 1. write data value 0x5a to hi-3210 memory address 0x8fff. 2. write data value 0xa5 to hi-3210 memory address 0x8fff. 3. apply a positive pulse to the prog input pin of at least 1ms. if the three-step sequence is interrupted by any intervening host activity between steps 1 and 2, or 2 and 3, or if the prog pulse is less than 1 ms, the programming cycle will not start and the device remains in the idle state. taking the prog pin low initiates the cycle. the ready pin goes low, and the contents of the hi-3210 memory and registers are copied to the eeprom. when copying is complete, the hi-3210 executes a byte-by-byte comparison of the eeprom and its own register / memory contents. if the verification completes successfully, the ready pin goes high. a 2?s complement of the checksum is also written to the eeprom, which is used during the auto-initialization sequence validation test. if the comparison of the eeprom contents and hi-3210 memory / register contents results in a discrepancy, the hi- 3210 enters the safe state, the progerr bit is set in the pending error register and the int output is asserted. the user must clear the progerr issue before normal operation can resume. programming the auto-initialization eeprom. reserved arinc 429 tx0 transmit schedule table reserved look-up tables 0x0000 0x3400 0x3fff 0x4000 0x47ff arinc 429 tx1 transmit schedule table arinc 429 tx2 transmit schedule table arinc 429 tx3 transmit schedule table 0x4800 0x4fff 0x5000 0x57ff 0x5800 0x5fff 0x6000 0x79ff 0x7a00 0x7bff configuration registers 0x8000 0x8xxx reserved 0x7c00 0x7fff 0x0000 0x3fff 0x3400 0x3fff 0x4000 0x47ff 0x4800 0x4fff 0x5000 0x57ff 0x5800 0x5fff 0x6000 0x79ff 0x7a00 0x7bff 0x7c00 0x7fff 0x8000 0x8xxx 0x33ff hi-3210 memory eeprom reserved reserved arinc 429 tx0 transmit schedule table reserved look-up tables arinc 429 tx1 transmit schedule table arinc 429 tx2 transmit schedule table arinc 429 tx3 transmit schedule table configuration registers holt integrated circuits 36 hi-3210
operating supply voltage temperature range industrial ......................... -40c to +85c extended ....................... -55c to +125c vdd....................................... 3.3 vdc 5% operating x x x supply voltage ( logic input voltage range power dissipation at 25c 1.0 w solder temperature 275c for 10 sec. junction temperature 175c storage temperature -65c to +150c vdd) -0.3 v to +5.0 v -0.3 v dc to +3.6 v parameter symbol condition min typ max units operating voltage vdd 3.15 3.30 3.45 v supply current idd 50 ma min. input voltage (hi) v digital inputs 70% v max. input voltage (lo) v digital inputs 30% v pull-up / pull-down current digital inputs and data bus 30 min. output voltage (hi) v i = -1.0ma, digital outputs 90% v max. output voltage (lo) v i = 1.0ma, digital outputs 10% v ih il oh out ih out dd dd dd dd i a pud vdd = 3.3 v, gnd = 0v, t = operating temperature range (unless otherwise specified). a dc electrical characteristics note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. recommended conditions absolute maximum ratings holt integrated circuits 37 hi-3210
ac electrical characteristics limits parameter symbol units min typ max spi host bus interface sck clock period t 50 ns hold time after last sck falling edge t 25 ns inactive between spi instructions t cyc ceh ce ce set-up time to first sck rising edge t 25 ns 100 ns spi si data set-up time to sck rising edge t 10 ns spi si data hold time after sck rising edge t 10 ns sck high time t 25 ns sck low time t 25 ns so valid after sck falling edge t 20 ns so high-impedance after inactive t 75 ns ces cph ds dh sckh sckl dv chz ce ce serial output timing diagram ce sclk so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance serial input timing diagram ce sclk si msb ces t ds tt dh lsb cph t ceh t vdd = 3.3 v, gnd = 0v, t = operating temperature range (unless otherwise specified). a holt integrated circuits 38 hi-3210
pin configuration for hi-3210, 64-pin qfn package notes 1 . all vdd and gnd pins must be connected. 2. see data sheet page 1 for hi-3210, 64-pin pqfp package configuration. holt integrated circuits 39 top view 48 arxbit3 46 atx0n 45 atx0p 44 atx1n 43 atx1p 42 atxslp1 41 vdd 40 gnd 39 arxbit2 38 atxslp2 37 atx2n 36 atx2p 35 atx3n 34 atx3p 33 atxslp3 47 atxslp0 arx7p 17 arx7n 18 mode0 19 mode1 20 mclk 21 arxbit0 23 vdd 24 gnd 25 arxbit1 26 hmiso 27 hsclk 28 hmosi 29 30 mint 31 mode2 22 mintack 32 hcsb aack 1 arxbit6 2 aint 3 arxbit7 4 scanshift 5 arx2n 6 arx3p 7 vdd 8 gnd 9 arx3n 10 arx4p 11 arx4n 12 arx5p 13 arx5n 14 arx6p 15 arx6n 16 hi-3210pcx 64 arx2p 61 arx0n 60 arx0p 59 scanen 58 arxbit5 57 ready 56 esclk 55 emosi 54 53 emiso 52 51 arxbit4 50 atxmsk 49 mrst 63 arx1n 62 arx1p run ecsb hi-3210
part package number description pq 64 pin plastic quad flat pack pqfp (64pqts) pc 64-pin plastic chip-scale package qfn (64pcs) part temperature burn number range flow in i -40c to +85c i no t -55c to +125c t no m -55c to +125c m yes part package number description blank tin / lead (sn / pb) solder f 100% matte tin (pb-free rohs compliant) hi-3210px x x ordering information holt integrated circuits 40 hi-3210
document rev. date description of change ds3210 new 5/10/11 initial release. revision history holt integrated circuits 41 hi-3210
bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .354 (9.00) bsc .039 (1.00) max .008 (0.20) typ .0197 (0.50) bsc .010 (0.25) typ .016 .004 (0.40 ) .10 .281 .003 (7.125 ) .075 .281 .003 (7.125 ) .075 bottom view top view .354 (9.00) bsc the metal heat sink pad on the bottom of the package is electrically isolated from the chip. it can be left floating or connected to vdd or gnd package type: 64pcs inches (millimeters) 64-pin plastic chip-scale package (qfn) holt integrated circuits 42 package dimensions 64 pin plastic quad flat pack (pqfp) inches (millimeters) package type: 64pqts .473 (12.00) bsc sq .063 (1.60) .02 (0.50) .009 .002 (0.22 .05) .008 (0.20) .055 .002 (1.40 .05) .004 .002 (0.10 .05) .394 (10.00) see detail a detail a 0 7 bsc sq max r max .003 (0.08) r min bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95)

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